What part of assembly are you interested in precisely? General knowledge in instructions? If so, add me on Discord - my username is the same as here.
Oddly I cannot "find" you on Discord. I am R3Z3N / .r3z3n
For example to choose where which boot firmware to compile in the OSDPAY.S file:
This is commented out for notes line 18
Code:
; This is the device the firmware will load BootManager from, if installed.
; Device
; 0 = Memory Card Slot 1
; 1 = Memory Card Slot 2
; 2 = USB HDD(requires USBD.IRX and USB_MASS.IRX to be stored at mc0:/BM/SHARED)
; 3 = CC2.0+ DataFlash(on-chip)
;
;BOOT_DEV EQU 0
so to concentrate on fixing Dev mode 2 (line 657 of OSDPAY.S) for and/or combination of maybe making a "boot order" (mind you I changed: txtMC0_USBMASS to txtMC0_USBHDFSD and its reference to the same pointed file name: (The drivers used are EL ISRAS BDM ASSAULT and work fine when BM is running, allowing me to use an exfat usbstick). Sadly dev mode 3 is kicked to OSDSYS (sony memcard manager and settings)
Code:
args_boot:
IF BOOT_DEV == 0
MESSAGE "Booting from Memory Card Slot 1"
ALIGN 4
DW txtROM0_XSIO2MAN, txtROM0_XMCMAN, txtBM_ELF
argc_boot: DW 3
txtBM_ELF: DB "mc0:/BM/BM2.ELF",0
ENDIF
IF BOOT_DEV == 1
MESSAGE "Booting from Memory Card Slot 2"
ALIGN 4
DW txtROM0_XSIO2MAN, txtROM0_XMCMAN, txtBM_ELF
argc_boot: DW 3
txtBM_ELF: DB "mc1:/BM/BM2.ELF",0
ENDIF
IF BOOT_DEV == 2
MESSAGE "Booting from USB"
ALIGN 4
DW txtROM0_XSIO2MAN, txtROM0_XMCMAN, txtMC0_USBD, txtMC0_USBHDFSD, txtBM_ELF
argc_boot: DW 5
txtBM_ELF: DB "mass:/BM/BM2.ELF",0
txtMC0_USBD: DB "-m mc0:/BM/SHARED/USBD.IRX",0
txtMC0_USBHDFSD: DB "-m mc0:/BM/SHARED/USBHDFSD.IRX",0
ENDIF
IF BOOT_DEV == 3
MESSAGE "Booting from CC2.0+ DataFlash"
ALIGN 4
DW txtBM_ELF
argc_boot: DW 1
txtBM_ELF: DB "dffs:/BM/BM2.ELF",0
BIN_IOPLOAD: INCLUDE BINARY "..\TMP\IOPLOAD.BIN"
ENDIF
And on the to the idea of boot order maybe something like:
Code:
args_boot:
IF BOOT_DEV == 0
MESSAGE "Booting from Memory Card Slot 1"
ALIGN 4
DW txtROM0_XSIO2MAN, txtROM0_XMCMAN, txtBM_ELFMC0
argc_boot: DW 3
txtBM_ELFMC0: DB "mc0:/BM/BM2.ELF",0
txtBM_ELFMC1: DB "mc1:/BM/BM2.ELF",0
ENDIF
Line 5 also references txtBM_ELF, so unsure then how to add a second "failover" or if not avaliable, try txtBM_ELFMC1 etc. Of course want to run first avaliable...not multiple
Code:
_bootOSD:
sltiu at, a2, 3
bnez at, _noError
nop
lw a0, 0x08(a3)
la a1, txtBM_ELF
jal strcmp
nop
bnez v0, _noError
nop
li at, 1
sw at, 0x08(sp)
So I updated a couple things, yet to push to github as I also broke something:
So when choosing firmware IE load from MC0/1/USB/HDD I had it write a message to screen to make sure BM and drivers were installed however the boot cd did not give that option. Changed the boot cd to show "Device Manager" which is were you install drivers. I will probably change it to "Device Drivers" or something.
Ie do this before restarting as otherwise have to reboot recovery/upgrade disc and do that...which requires pressing reset 6x. Will want to make sure BM displays this info.
MC0/MC1 choices finalized and working great.
However broke boot cd now not showing usb or hdd when trying to flash fw from those sources....
USB/HDD preliminary support working....at least mass:/BM/BM2.ELF or pfs0:/BM/BM2.ELF runs. However once ran, Boot Manager from these sources does not actually have access to the scripts needed for the menus....(everything is an editable script for Boot Manager, which makes this awesome)
Also started work on including base apps like wLE ISR, KHN, OPL and choices as to run the Memory Module shutdown, drivers off, and normal. Cool thing is these individual choices can be autobooted, or shortcuts IE L1 can be wLE ISR with drivers off (because all the needed drivers are built into the ELF.
Sooo I think I have CCHW.S working to autodetect which DataFlash size is used when I do it by hand. Following along with ChatGPT works so far. Still waiting for my CC2.0 with 8MB dataflash back.
Opcode D7H calls a status register (Section 11-4 in the dataflash manual), and bits 5 through 2 identify storage size, however they mean nothing in decimal:
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
RDY/BUSY COMP 1 0 1 1 PROTECT PAGE SIZE
So the firmware shifts right 3, and drops bits 7 through 3.
For example
10011100 becomes
00010011 becomes
00000011 which is 0x02 in hex (0x means hex, and would also ending in H like D7H above)
CC Team notes: xxxkb is dataflash size /xxx is page size
Code:
;001 - 512 /264 0x01
;010 - 1024/264 0x02
;011 - 2048/264 0x03
;100 - 4096/264 0x04
;101 - 4096/528 0x05
;110 - 8192/528 0x06
The AT45DB dataflash family has 6 models.
Code:
Model Size Page
AT45DB021D 128KB 264
AT45DB041D 512KB 264
AT45DB081D 1MB 264
AT45DB161D 2MB 528
AT45DB321D 4MB 528
AT45DB642D 8MB 1056
So the comments have 3 things wrong right off the bat. There are not 2 models of the 4MB and the 8MB is actually 1056-byte pages! The 2MB is also a 528-byte page! Is this why the CC 2.0 SLE sometimes loses its firmware? Because when running the D7H opcode, the 2MB gets a 264byte page assigned to it! :-(
So when looking here are the expected values:
Code:
; AT45DB Family D7H Opcode Section 11.4
; Bits 5 through 2 indicate size but have no meaning in decimal
; Shift Right 3, and mask lowest 3 bits
; AT45DB041D 10011100 gets converted to 011 0x03 DF_Page264
; AT45DB081D 10100100 gets converted to 100 0x04 DF_Page264
; AT45DB161D 10101100 gets converted to 101 0x05 DF_Page528
; AT45DB321D 10110100 gets converted to 110 0x06 DF_Page528
; AT45DB642D 10111100 gets converted to 111 0x07 DF_Page1056
So 2 things, let's correct what the firmware does to what it should and add code to run the branch for a 1056-byte page dataflash!
Code:
IF _F_CC_DF_Detect
; v3 of 1056-byte page testing
; AT45DB Family D7H Opcode Section 11.4
; Bits 5 through 2 indicate size but have no meaning in decimal
; Shift Right 3, then mask lowest 3 bits
; AT45DB041D 10011100 011 0x03 DF_Page264
; AT45DB081D 10100100 100 0x04 DF_Page264
; AT45DB161D 10101100 101 0x05 DF_Page528
; AT45DB321D 10110100 110 gets 0x06 DF_Page528
; AT45DB642D 10111100 111 gets 0x07 DF_Page1056
CC_DF_Detect PROC
addiu sp, sp, -0x10
sw ra, 0x00(sp)
nop
bual CC_DF_ReadStatus
nop
srl t1, v0, 3 ; Shift right by 3 bits
andi t1, t1, 0x07 ; Mask the lowest 3 bits
sltiu at, t1, 0x05 ; Check if t1 < 5
bnez at, _set_264bytes
sltiu at, t1, 0x07 ; Check if t1 < 7
bnez at, _set_528bytes
; Default case for 1056 bytes
li t2, 1056 ; Set page size for 1056-byte dataflash
la t3, DF_Page1056 ; Set DF_Page handler for 1056-byte dataflash
b _done
_set_264bytes:
li t2, 264 ; Set page size for 264-byte dataflash
la t3, DF_Page264 ; Set DF_Page handler for DF_Page264
b _done
_set_528bytes:
li t2, 528 ; Set page size for 528-byte dataflash
la t3, DF_Page528 ; Set DF_Page handler for DF_Page528
b _done
_done:
la v0, dfdev
sw t2, 0x00(v0)
lw ra, 0x00(sp)
sw t3, 0x04(v0)
jr ra
addiu sp, sp, 0x10
CC_DF_Detect ENDP
ENDIF
TLDR:
If masked bits are less than 5, set t1 to 264 branch
Otherwise if includes 5 or 6, set to 528 branch
If 7 or greater set to 1056 branch
and then we need the code for the DF_PAGE1056 code:
Code:
DF_Page1056 PROC
andi v0, a2, 0xFF
sll v0, v0, 8 ; v0 = (baddr & 0xFF) << 8
srl a2, a2, 8
andi a2, a2, 0x07 ; Mask the top 3 bits for 1056-byte addressing
or v0, v0, a2
sll v1, a1, 3 ; Shift paddr left 3 bits
andi v1, v1, 0xF8 ; Mask for alignment
or v0, v0, v1
sll v0, v0, 8
srl a1, a1, 5 ; Shift right for remaining bits
or v0, v0, a1
sll v0, v0, 8
jr ra
or v0, v0, a0
DF_Page1056 ENDP
Simplified page detection logic down to 33 lines from almost 50....
