Has anybody discovered how to undervolt Cell or RSX?
- Thread starter raidriar
- Start date
villahed94
Member
I replaced 2 Tokins and the ripple was so much better:
It allowed me to go even lower, and discovered the true crash point for my CELL (The point where a BE Deadlock occurs). It was 0.965V
I therefore moved it up a notch and it's been stable so far at 0.98V measured.
@RIP-Felix
IMO the benefits of this modification are severalfold:
- Undervolt : Lower power draw= Less thermal and electrical stress for all components involved.
- Undervolt: Will help weed out good and bad chips for OC before actually committing to an OC FW.
- Overvolt: For those who want to try higher CELL speeds, preferably after determining chip quality by undervolting.
NightLess
Member
The two Frankies I used could not run stably below 1.0v. They seemed to be 2006 CELLs? I didn't care. Maybe yours is a silicon lottery? Felix should be interested in this.I replaced 2 Tokins and the ripple was so much better:
It allowed me to go even lower, and discovered the true crash point for my CELL (The point where a BE Deadlock occurs). It was 0.965V
I therefore moved it up a notch and it's been stable so far at 0.98V measured.
@RIP-Felix
IMO the benefits of this modification are severalfold:
I can assume a frankie'd system with a golden CELL (one that can run below 1V) and a 40nm RSX can definetly do 100W or less.
- Undervolt : Lower power draw= Less thermal and electrical stress for all components involved.
- Undervolt: Will help weed out good and bad chips for OC before actually committing to an OC FW.
- Overvolt: For those who want to try higher CELL speeds, preferably after determining chip quality by undervolting.
RIP-Felix
Senior Member
Yeah, don't do that. Sony should be ashamed of themselves for that one. It was not repair. It was coping out!
Well cat's out if the bag on the CELL offset for VID. M4j0r suggested I check 3110 and 3111 when looking for RSX VID. I tried 3110 first and it didn't change the RSX voltage I was probing. I didnt think to check the CPU voltage, or I would have noticed. But now that you confirmed that's where CELL VID is, it makes sense. Nice job!
Well, I did want to get around to undervolting to see how much headroom there is on retail chips. I suspected there was quite a bit. The "bined" 90nm RSX that run significantly cooler are actually running at a lower VID. Makes sense huh?
So cool, we can VID bin any 90nm RSX now to reduce how hot it runs and hopefully without stability issues. I do want to get these results, I've just been swamped with work and projects. So never seem to find the time.
Also, reduce your vertical scale to 50mV/div, and horizontal to between 1 and 5us. it makes the ripple more accurate and aligns with the scale I've used previously. Will make for better comparisons.
Starship2
Member
Thats cool. this is doing so much in terms like reliability. maybe it will also help us with overclocking the cell one day. now we have to do the job on sherwood where it follows the same principle, i think.
villahed94
Member
I personally don't own a Sherwood system (..yet) but I assume the addresses must be similar (RSX address -1 ).
Will be interesting to see how later systems react to the CELL undervolting, though this is huge for Phats because this will prevent senseless kills by failed delids (ask me how I know).
Starship2
Member
i do have some. i will take a look at one of them and see how it reacts. in sherwoods RSX is located at 0x51 so i will take a closer look at 0x50. the value should be FF.
i was thinking wrong when i assumed Cell VID at 0x310E as i remebered that the value for stock VID is FF. i was concentrating on numerous values what doesnt go to plan in this case.
next question is if we can translate the Cell VID Values exactly the same way as for the RSX. If so we can use one VID Table for both. at first glance it looks like theyre identical.
RIP-Felix
Senior Member
RSX and CELL use the same mosfet driver and VRD tables. So the same tables I made for the RSX should translate to CPU as well. Mullion and Sherwood.
Beware tho, if your CPU needs delided, this doesn't magically fix the paste. If it's overheating or throwing errors related to thermal monitors or thermal panic lowering core voltage is only going to slow how much heat builds. It might change the error that occurs or forstall an overheat event, lower total fan% at temp, and so on, but it's still got inefficient paste and needs a delid.
Basically I see this a way to lower fan% and make the console quieter. Just chills the Cell out a bit. If the RSX in your unit is what's leading Fan% this wont change anything. The CELL is a tank and can easily take the temps it runs at normally, so it doesn't really need lower temps. It's not defective like the the 90nm RSX is.
If you do this, it's mainly for the fan% gains. IG it could help the CPU last a bit longer. Also, if we ever get a CPU OC now we know how to boost voltage.
Beware tho, if your CPU needs delided, this doesn't magically fix the paste. If it's overheating or throwing errors related to thermal monitors or thermal panic lowering core voltage is only going to slow how much heat builds. It might change the error that occurs or forstall an overheat event, lower total fan% at temp, and so on, but it's still got inefficient paste and needs a delid.
Basically I see this a way to lower fan% and make the console quieter. Just chills the Cell out a bit. If the RSX in your unit is what's leading Fan% this wont change anything. The CELL is a tank and can easily take the temps it runs at normally, so it doesn't really need lower temps. It's not defective like the the 90nm RSX is.
If you do this, it's mainly for the fan% gains. IG it could help the CPU last a bit longer. Also, if we ever get a CPU OC now we know how to boost voltage.
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villahed94
Member
From my testing lower CELL temps also led to (slightly) lower RSX temps as well.
Even though they are in theory cooled by separate heat pipes, they share thermal dissipation on the PCB and through the heatsink (because of the single fan and all)
Sure if the paste is bad it will need replacing, but it will make it exhibit much less overheating and also make the systems with good paste last longer with it.
From my tests with a pure 90nm system, the power consumption went from 200-ish W down to 135-ish when undervolting both. A 65W reduction (or 32%) in total power draw.
Since the system I got has a lousy bin 90nm RSX that also has had a history of 3034, I'll have it Frankie'd ASAP with a 40nm RSX. Then I'll try the double whammy ( Mild OC of 700/850 and Undervolt).
Sampsonay
Member
This console is delidded but is otherwise stock. Absolutely wild results over here.https://i.imgur.com/8nqLtUm.jpeg
Starship2
Member
Thats a valid point we should keep in mind. High Cell temps will always affect RSX and pull its temp higher due to dissipation over the mainboard.
I remember having a console where cell was running over 80C (Thermalpaste not wearing),
lowering it to ~65C at same fan speed did also lower RSX temp 3-5C whats a potent amount. Hypothetically spoken undervolting both chips may keep 90nm's drastically longer alive. Imagine having 2 good responding silicon winners running on low voltage, how low will temperatures be? Its definetly under 60C @ 30% fan. And we didnt even talk about frankie's. It would be easily possible to keep it at low fifties. That would increase lifespan of tokins and rsx significantly.
villahed94
Member
Which were your temps before the procedure and which voltages did you achieve?
Sampsonay
Member
This particular CELL went from 1.16V to 1.06V. RSX went from 1.28V to 1.12V. Also the CELL / RSX temps before used to peak around 73C/65C and 28% fan speed.
villahed94
Member
I would assume yes as long as you have R/W access to Syscon . However I wouldn't recommend it because you can softbrick your console if you set an unstable voltage, until you go into Syscon and rewrite to a higher value.
villahed94
Member
IIRC , and correct me @RIP-Felix if I'm wrong, but the voltage mod is for the GDDR, to prevent burning it.
However, it would also help. Does anybody with 65 and 40nm RSX native systems have the default voltage for those?
RIP-Felix
Senior Member
When the paste has good contact the exhaust is like 40-45C. That's mostly from the CELL, 100ish watts vs the RSX's 65. So that exhaust is essentially warming the RSX's heatsink and preheating the IHS's starting temp to 40-45C.
The 40nm RSX usually tops out in a frankie to between 53-56C. So it only heats about 10C above the starting temp the cells exhaust back feeds it to. So if you can reduce the cell's temps and amount of heat the HS back heats the RSX, the RSX should decrease some also.
The 40nm RSX usually tops out in a frankie to between 53-56C. So it only heats about 10C above the starting temp the cells exhaust back feeds it to. So if you can reduce the cell's temps and amount of heat the HS back heats the RSX, the RSX should decrease some also.
Yes, that's a legitimate strategy to reduce the ripple the toki s see. The reduced current load of a lower voltage will reduce the amplitude of voltagw spikes. We could probably prevent a YLOD that was caused by a bad Tokin by reducing the voltage. That might make it stable enough to boot and get saves off, etc.
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NightLess
Member
Well, voltage MOD reduces the voltage of VDDR, and what we change through VID is the voltage of VDDC, which means that Frankenstein's voltage MOD only reduces the voltage of RAM, and the core voltage is not changed?
RIP-Felix
Senior Member
No, I asked @M4j0r about that once and while I don't claim to understand what he told me, it was something to the effect of 'there's alot that needs to happen before that can happen.' I get the gist that it's not worh the effort, but not impossable.
The VDDR Voltage reduction is different than the VDDC core voltage we're talking about here. RSX_VDDR is the refrence voltage for the FlexIO. I think it's the RSX's interface controller. It's independently powered vs the Cell/SB FlexIO refrence voltage (YC_RC_VDDIO). I think the reasonnis so the RSX's connection in the FlexIO can be sequenced as it's brought online in a distict stage after the Cell and SB are.
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