PS2 HDD for PS2 SCPH75000x & later models

@wisi Could you please tell me which contacts of your cpld xc9572xl go to the console, and which to the hard drive. And do you still have the firmware that is hardwired into cpld? And what program did you use to flash cpld?Сan I flash this cpld using a programmer on FT2232H, the datasheet indicates that it can work with the jtag interface. https://www.ftdichip.com/Support/Documents/AppNotes/AN_129_FTDI_Hi_Speed_USB_To_JTAG_Example.pdf Just at the moment it would be the most reasonable solution - to make the same adapter as yours and try (test) its operation, you provided me with a lot of useful information regarding the bus interface, the operation of modules, but I still don't understand anything about this.
 
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I don't think the FTDI chip will work, unless it can play SVF files.
The software used was Xilinx ISE v14. I used the Xilinx Parallel Cable III as interface ('programmer'). You can also use anything that can play SVF files too (which includes a lot of stuff, including MCUs). I once made a SVF player using the SIO0 interface of the PS2, but that implementation was very hacky, even if it did actually work (it required almost no external components).

The source was the schematic you see in the pictures. If you copy the same schematics in the Xilinx ISE (or better yet, rewrite it in Verilog) it should mostly work. Would certainly require some debugging.
I have the original files of course, so I guess I could upload them too...

It is mostly self-explanatory which signals go t PS2 SSBUS and which to the HDD PATA interface, as they match by name.
PS2_SRD ... goes to /SRD of the PS2...
PS2_CS1 - /CS1 (DVD ROM)
PS2_CS2 - /CS2 (unused) (BOOT ROM)
PS2_SRDOUT - to the /SRD input of the BOOT ROM (which should be disconnected, so we don't bus-fight with the BOOT ROM).
(Not necessary if another interface is used - say /EXTR).
PS2_CS8 - /EXTR
PS2_SWR - /SWR
DBG0, DBG1 - to LEDs and through resistors to Vcc (for debugging)
PS2_D(7:0) lower 8 bits of the data bus
PS2_DH(7:0) high 8 bits (15:8) of the data bus
PS2_DACK - from the /DACK of the SSBUSC channel used
PS2_DREQ - to /DREQ ...
PS2_INT - to a selected interrupt line (/INT_EX for example)

PATA / IDE:
IDE_DL(7:0) ... obvious
IDE_DH(7:0) again, but the high 8 bits to ATA HDD/CDVD/whatever
nRESET, DA0, DA1, DA2, nCS0, nCS1, nDIOR, nDIOW, INTRQ, nDMARQ, nDREQ - to/from ATA interface


But this all should be considered more of an example, and if you don't have a clear idea on how to debug it and fix any potential problems, maybe better try with the NetworkAdapter as you originally planned.
 
@wisi my network adapter is not original, but a clone of GameStar on a ps2Run microcircuit (maybe it's a cpld).To try it, I still haven't figured out where to find the ssbusch service to edit it (for example, in the Launch.elf program), but I'm also considering the option with cpld
 
AFAIK the ps2Run chip is not programmable but an ASIC. Only earlier adapters had programmable FPGAs.
This shouldn't affect compatibility too much...

You have to edit the DEV9 and ATAD IRX modules or you can do the test with only code from EE side too.
You don't really need to edit SSBUSC IRX.
SSBUSC.IRX source code can be found in the modelues from [RO]man and later in fps2bios - https://github.com/mirror/pcsx2/tree/master/fps2bios The one used is the one from the PS2 BOOT ROM. Basically you don't need to edit it.
ATAD and DEV9 in the PS2SDK - https://github.com/ps2dev/ps2sdk/tree/master/iop/dev9
 
It is not built-in on that model. It is not a standard PPC in any way. It is an integrated ASIC - much more a PPC core with a lot of the IOP peripheral HW inside.
 
@wisiIt is necessary in those two modules to change the memory address from DEV9 to DEV5, and also to replace the strobe signals DEV9 with DEV5, right? Group PS2 Heavy Gamers (link to it is in PS2 DEV VIKI).
 
Yes, more or less. Maybe to Dev8 (EXTR) but you could use Dev5... as long as nothing else uses it.
 
@wisi DEV8 is absent in models 790000 and 90000 (at least I don't know where to find signals, since there is no information on this consoles), but DEV5 signals are available on cxd3098q
 
OK. I guess it is missing on some of them. But for Dev5 you will have to make sure CDVDMAN and other code (like OSDSYS) is not accessing Dev5. You can alternatively map SPEED higher in the same memory range, which should avoid problems to some extent.
 
Hi there! Sorry for necropost but i searching a way to connect HDD to 9000 and found this thread. Is ps2madd project left unfinished or somebody got it to work? Is there a wiring diagrams exists? wisi?
 
The schematic of the CPLD internal logic of PS2MAdd is attached to this post:
https://www.psx-place.com/threads/hdd-for-ps2-scph75000x-later-models.30696/page-2#post-254935

The necessary code should be in the DECKARD added library, attached to this post (I haven't checked in what state it might be; it was long ago):
https://www.psx-place.com/threads/hdd-for-ps2-scph75000x-later-models.30696/page-2#post-255399

It is unlikely I will work on a newer version anytime soon. Thank you for the interest though.
 
Vincent7 said:
Can you provide soldering diagram of that ps2madd device for ps2's PCB?
Click to expand...
It would also be interesting to see the soldering scheme, but I think the speed of this device will be a little better than usb/mx4sio, maybe as on smb, but it cannot be compared to the speed of fat models and 70 models - just half of the addresses were used (8 out of 16) and the mode pio, not dma. I suggested using the dev5 interface - however, this requires software writing of code, and as far as I understand - it is necessary to write a lot of lines of code, as well as to understand how it all works, because in fact, in this case, we create an optical drive emulator
 
Vanja_Mileshovskyj said:
It would also be interesting to see the soldering scheme, but I think the speed of this device will be a little better than usb/mx4sio, maybe as on smb, but it cannot be compared to the speed of fat models and 70 models - just half of the addresses were used (8 out of 16) and the mode pio, not dma. I suggested using the dev5 interface - however, this requires software writing of code, and as far as I understand - it is necessary to write a lot of lines of code, as well as to understand how it all works, because in fact, in this case, we create an optical drive emulator
Click to expand...
But wisi said with that device HDD works just like on fat ps2 models
 
On DECKARD models, the added code on DECKARD emulates the HDD so it looks to the PS2 the same way as the internal HDD but the speed is not the same. The internal HDD can reach 50MB/s to/from the EE (66 MB/s even to/from the IOP), while this reached something around 5 or 8MB/s, but it was too long ago and I don't remember. It can in theory be made faster even with a narrow bus, as long as the logic is more and there is space for a FIFO.
The internal CPLD logic shows the names of the lines which connect to the PS2, so the connection to the PS2 depends on that and can be determined from that. Because the idea is to be able to use either only the BOOT/DVD ROM lines or the EXTR lines or the CDVD SSBUS channel lines, it is not specified quite exactly which of them is used. It is mostly the same for all (the ROMs lack DMA of course).
Whoever wants to make it would have to customize it based on what they want and what points are exposed on the PS2 they are mounting it on.
The CPLD logic needs to be rewritten in Verilog and bigger PLD/FPGA needs to be used. And many other things fixed too. So it is not something simple. In fact it is just the fact that there are so many options that makes it difficult because I would like to support most of them but that is difficult.
 
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