For QFN80 variant of RP2350, 48 GPIO are available in bank 0 and 6 GPIO are available in bank 1.
However, the bank 1 GPIO can not use PIO.
There are 43 SSBUSC related connections, so 5 of them remain in bank 0. 32 of them (address+data lines) need to be together for best Extra Wide DMA performance.
Usually, 6 lines are used for QSPI flash.
By replacing QSPI flash with SPI flash that can free up 3 lines in bank 1.
/CSRST and /CRST can be handled by CPU instead of PIO so 2 lines in bank 1 can be used.
As a result, 7 lines can be available in bank 0.
For connecting a 4-bit SDIO device, 6 lines are needed.
A line in bank 0 or 1 could be used for a TXS02612 port expander to switch between two devices.
Another line could be used to switch between 3.3v and 1.8v.
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RP2350 can be overclocked pretty far:
https://forums.raspberrypi.com/viewtopic.php?t=375975