PS3 Ram Upgrade on fat Models

Starship2

Member
I was wondering if it is possible to upgrade ram on fat models. fat model mainboards do have quad rams and newer slim consoles have dual rams, but doubled size. quad ram ist 4x 64mb and dual is 2x 128mb. looks like both have 104pin bga. wouldnt it be possible to put 4 128mb ramchips from slim models on fat mainboards?
i had to think about ram upgrade on 1.6 xboxes as it was possible to place one ramchip on another and just lift the chipselect pin of the added chip. with this simple trick the cpu addresses both chips as one, just doubled size. if its that easy, it should work on ps3 too without any problems. does anybody have reliable information about the pinout? registers etc should be identical for obvious reasons.


Fat Models
X5116AC-3C-E.jpg



Newer slim models
Elpida_X1032BASE-3CA2-F.jpg
 
I didn't know that about the 360, but as you no doubt know, sometimes it doesn't allow for such a thing. report back if you can/once you find out, if not here, somewhere else.
 
I didn't know that about the 360, but as you no doubt know, sometimes it doesn't allow for such a thing. report back if you can/once you find out, if not here, somewhere else.
Not the 360. im talking about xbox classic's 1.6 late models. If pinout is the same, that should work on ps3.. would be a cool thing
 
Even if works, nothing will address it beyond 256. You need dedicated homebrew, so first also sdk changes. The same was on XC, only XBMC, UX, current modern stuff and few emulators supporting it.
 
Even if works, nothing will address it beyond 256. You need dedicated homebrew, so first also sdk changes. The same was on XC, only XBMC, UX, current modern stuff and few emulators supporting it.
Yeah right, but thats a minor problem. Community is extremely strong when it comes to software as we have some really good devs. i mean its fucking worth it. We have enabled 8th spe without any advantages so why shouldnt we focus on sth like that? Imagine what kind of battleship ps3 can become. Rsx even uses xdram so this could be a thing maybe.
 
although I didn't have an xbox, I was able to compile super mario 64 for it, two versions. one was the regular version; the other a souped up version. I just checked. I still have them both on my pc. I had to have someone else check them for me. the basic version he said had sound problems; the other was perfect. it's called xsm64, I believe: https://github.com/mborgerson/xsm64

those are the instructions. I still have it:
 

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although I didn't have an xbox, I was able to compile super mario 64 for it, two versions. one was the regular version; the other a souped up version. I just checked. I still have them both on my pc. I had to have someone else check them for me. the basic version he said had sound problems; the other was perfect. it's called xsm64, I believe: https://github.com/mborgerson/xsm64

those are the instructions. I still have it:
Nice work. Im not that much into software, but hardware. Its crazy what some people can do with software.
 
I was wondering if it is possible to upgrade ram on fat models. fat model mainboards do have quad rams and newer slim consoles have dual rams, but doubled size. quad ram ist 4x 64mb and dual is 2x 128mb. looks like both have 104pin bga. wouldnt it be possible to put 4 128mb ramchips from slim models on fat mainboards?
i had to think about ram upgrade on 1.6 xboxes as it was possible to place one ramchip on another and just lift the chipselect pin of the added chip. with this simple trick the cpu addresses both chips as one, just doubled size. if its that easy, it should work on ps3 too without any problems. does anybody have reliable information about the pinout? registers etc should be identical for obvious reasons.


Fat Models
X5116AC-3C-E.jpg



Newer slim models
Elpida_X1032BASE-3CA2-F.jpg


You'll also need a "Hybrid Firmware" for it using some of DECR CoreOS to support the double amount of RAM.
 
Nice work. Im not that much into software, but hardware. Its crazy what some people can do with software.

coding is beyond my abilities, but I can at least follow directions or make changes to code when indicated. this is coming from someone who knew nothing about hacking years ago, didn't know how to hex, compile, or even use photoshop back then either.
 
You'll also need a "Hybrid Firmware" for it using some of DECR CoreOS to support the double amount of RAM.
Youre right, we would have to create something special there.
When i get my bga reworkstation i will start an approach and see what happens. I will do some comparison on ram bga to see if its identical amount of pins. If so, ill solder 4 slim ramchips to a fat motherboard. Luckily i have enough donor and practicing boards to do so.
 
Youre right, we would have to create something special there.
When i get my bga reworkstation i will start an approach and see what happens. I will do some comparison on ram bga to see if its identical amount of pins. If so, ill solder 4 slim ramchips to a fat motherboard. Luckily i have enough donor and practicing boards to do so.

Good Luck and let us know about the progress
 
Good Luck and let us know about the progress
sadly, i have some bad news. i desoldered ram chips from a harvested fat and slim and compared the chips. chips are exactly same size.
but bga is different, fat has 104pin and slim has 150 pin layout. rambus is 16 bit on fats as it is 32bit on slims. i measured ram voltage and it is 1.8v on fat models, while we have 1.5v on slim. that would be easy to fix with a resistor replacement. i did some research if there are other ramchips with these specifications, 16 bit, 400mhz, 1.8v, 128mb with 104 pin bga. didnt find anything. laptop ram is too big as they come with many gigabytes. i thought if maybe xbox360 ram could fit, didnt find any specifications but i think they are different. so it seems impossible yet. i will keep an eye on that and maybe some day i'll find ramchips that match.
would have been a pretty cool mod and i didnt expect sony changing that much on these chips..
 
The (ED)X1016BASE-3CA2-F (1Gbit) does have a 104-FBGA package just like the 512Mbit models. However, it is unknown whether the pinout is the same: https://x.com/MinaRalwasser/status/1104741143114338309 .
There's no information because you had to "ask" for the datasheet: https://web.archive.org/web/20130829060916/http://www.elpida.com/en/products/xdr.html .
maybe we have to dig a little deeper. im pretty sure ram from ps3 isnt the only one in the world with these specs/pinout. there has to be another device with these chips, for sure. just have to find out..
that would be the last insane mod ps3 needs to have.
 
I actually attempted this few months ago, Research the pinout of both old and new chips, software side, then designed interposer pcb and stencil. But fails at almost last part: actual solder it.

XDR ram is actually simple (in trace routing perspective). easier than DDR actually. There is no need to do trace length matching at all, chip will handle that by itself. Pinout also simple.
All cell do have two XDR channel 32-bit each.
In early version, it uses four 64MiB 16-bit each while later board only use two 128MiB 32-bit instead. Of course it will have more pin.

DECR uses eight 64MiB 16-bit chips but run in 8-bit mode.

Here is schematic, you will see it is very simple. Just float last half of DQ/DQN pins. 32 bit ram chip can also run on 16 bit mode. We just need to tell it. Cell can do that with suppiled configuration.
chrome-Lr-KEh8d32-X.png

And some of pcbs and ram (pulled from junk testbench board. yes i am the owner of those). There is more pcb design outside this.

I design these for DIA board, these board do have two chip on each side, so it will have more space.

2024-11-11-15-40-17-498.jpg

kicad-c5f0-R43-P6-A.png

But sadly i'm unable to reball it properly yet, so i gave up for now.

But even in case if soldering part succeed, syscon firmware must also patched. Since its configuration are hardcoded inside. Including total amount of chip, bits per chip and size of each chip.

I dumped my XDR configuration from my own DECR-1000 and DIA-001/VER-001 board to compare difference here: https://www.psdevwiki.com/ps3/XDR_Configuration

I also use that DECR as a testbed. Since it can patch and recover easily.

I strongly believe it can fit all 4 patchable address. Most difference bytes have no effect and will still boot normally after change.

Very last few bytes maybe vendor related, but not confirmed. Some dumps are
10 23 28 while some 3F 23 28. Both value are found on retail dumps.
DECR-1000 always use 3F so I attempted to change it to 10, but it fails to boot. So i suspect this maybe vendor related.

Now, if all of above succeed and lv1 can see 512MiB ram, It will only useful on otheros but not in game. We also need to run decr firmware on it to access more ram in game aka DIY DECR-1400. Can this happen?
 
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I actually attempted this few months ago, Research the pinout of both old and new chips, software side, then designed interposer pcb and stencil. But fails at almost last part: actual solder it.

XDR ram is actually simple (in trace routing perspective). easier than DDR actually. There is no need to do trace length matching at all, chip will handle that by itself. Pinout also simple.
All cell do have two XDR channel 32-bit each.
In early version, it uses four 64MiB 16-bit each while later board only use two 128MiB 32-bit instead. Of course it will have more pin.

DECR uses eight 64MiB 16-bit chips but run in 8-bit mode.

Here is schematic, you will see it is very simple. Just float last half of DQ/DQN pins. 32 bit ram chip can also run on 16 bit mode. We just need to tell it. Cell can do that with suppiled configuration.
chrome-Lr-KEh8d32-X.png

And some of pcbs and ram (pulled from junk testbench board. yes i am the owner of those). There is more pcb design outside this.

I design these for DIA board, these board do have two chip on each side, so it will have more space.

2024-11-11-15-40-17-498.jpg

kicad-c5f0-R43-P6-A.png

But sadly i'm unable to reball it properly yet, so i gave up for now.

But even in case if soldering part succeed, syscon firmware must also patched. Since its configuration are hardcoded inside. Including total amount of chip, bits per chip and size of each chip.

I dumped my XDR configuration from my own DECR-1000 and DIA-001/VER-001 board to compare difference here: https://www.psdevwiki.com/ps3/XDR_Configuration

I also use that DECR as a testbed. Since it can patch and recover easily.

I strongly believe it can fit all 4 patchable address. Most difference bytes have no effect and will still boot normally after change.

Very last few bytes maybe vendor related, but not confirmed. Some dumps are
10 23 28 while some 3F 23 28. Both value are found on retail dumps.
DECR-1000 always use 3F so I attempted to change it to 10, but it fails to boot. So i suspect this maybe vendor related.

Now, if all of above succeed and lv1 can see 512MiB ram, It will only useful on otheros but not in game. We also need to run decr firmware on it to access more ram in game aka DIY DECR-1400. Can this happen?
Very good work and research. are you really sure about 16bit channels on quad configuration? i did some research too and have read from an engineer that quad config also uses 32 bit. not sure how reliable this information is, but maybe thats a thing.
at least it sounds doable. i expected it to require some really good solder skills. you shouldnt give up on that one
 
Very good work and research. are you really sure about 16bit channels on quad configuration? i did some research too and have read from an engineer that quad config also uses 32 bit. not sure how reliable this information is, but maybe thats a thing.
at least it sounds doable. i expected it to require some really good solder skills. you shouldnt give up on that one

Maybe you're misunderstanding my post, "four 64MiB 16-bit" mean four 16-bit chips total on the board. Each channel of cell have two chip connected to. Cell have two channel 32-bit each, this means 64-bit total, 64 DQ/DQN pins. Perfectly fit all the chips.

Bits is all about bandwidth, 64-bit total is maximum that cell can do. You can use bigger chips, more bits but there is no more DQ pin on cell to be connected to so it must left float. Then configure each chip to run at lower bandwidth/bits. You will get more capacity but total bandwidth still same.


XDR-quad_to_CELLBE_to_SouthBridge_diagram.png
 
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